1. Field of the Invention
The present invention relates to linear regulators of the type including a power MOS transistor intended to be connected, in series with a load to be supplied, between two D.C. terminals, the power MOS transistor being controlled by an amplifier-regulator for regulating the voltage across the load to a predetermined value. The present invention more specifically relates to linear regulators of the type having a low series voltage drop, that is, in which the voltage drop in the power transistor is minimized. Among these, the present invention more specifically relates to linear regulators of the type selecting the output voltage level, that is, including, in the regulator feedback loop, a circuit of switchable resistors for selecting one resistive path or another according to the desired output voltage.
2. Discussion of the Related Art
FIG. 1 shows an example of a conventional diagram of a linear regulator of the type to which the present invention applies.
Regulator 1 is essentially formed of a power MOS transistor 2, for example with a P channel, connected between a terminal 3 for application of a more positive supply voltage (Vbat) and an output terminal 4 of regulator 1. Terminal 4 is intended for being connected to a first terminal of a load (Q) 9, the other terminal of which is connected to a terminal 6 of application of a more negative supply voltage, for example the ground. A capacitor C is connected in parallel on load 2 to filter and stabilize output voltage Vout of regulator 1.
Power transistor 2 is controlled by a differential amplifier 5, an inverting input 7 of which receives a reference voltage Vref, generally provided by a voltage reference circuit of bandgap type or any other type of generator of a steady and precise voltage, and a noninverting input 8 of which receives, via a switchable resistor circuit 10, output voltage Vout.
In the field of application of the present invention, the regulator feedback loop applies a proportionality coefficient to voltage Vout, which depends on the desired output voltage level. It should thus be noted that the present invention applies to linear regulators in which output voltage Vout is greater than the reference voltage to enable lowering the voltage level of the non-inverting input of amplifier 5.
In linear regulators with several selectable output voltages, it is preferred to use a network of switchable resistors in the feedback loop rather than on the reference voltage application input. Indeed, this reference voltage is desired to be as precise as possible and is generally used by other regulators of the system and must thus keep a fixed value.
In the example shown in FIG. 1, regulator 1 can provide two distinct voltages according to the configuration in which circuit 10 is placed. Circuit 10 is formed, for example, of three resistors R1, R2, and R3 in series between terminal 4 and the ground. The junction point 11 of resistor R1 and resistor R2 is connected, via a first MOS transistor 12, for example with an N channel, to non-inverting input 8 of amplifier 5. The junction point 13 of resistor R2 and resistor R3 is connected, via a second MOS transistor 14, for example with an N channel, to non-inverting terminal 8. The respective gates of transistors 12 and 14 receive logic control signals CTRL1 and CTRL2 to select the resistive ratio of dividing bridge R1-R2-R3 according to the respective states of transistors 12 and 14. For example, for the regulator to provide a voltage Vout of the higher level, transistor 12 is off and transistor 14 is on, the respective control signals CTRL1 and CTRL2 of transistors 12 and 14 being low and high. To switch to a voltage Vout of lower level, transistor 14 is turned off and transistor 12 is turned on, by inverting the respective states of signals CTRL1 and CTRL2.
A problem that is raised in this type of regulator is that overvoltages on output Vout often appear upon changes of reference by switching of the transistors of circuit 10. Indeed, as one of transistors 12 and 14 is switched on and as the other one is switched off, amplifier 5 is abruptly unbalanced and will thus try to be balanced again by, for example, having voltage Vout rise from one level to another until non-inverting terminal 8 of amplifier 5 returns back to the voltage of balance with voltage Vref. However, part of the current that flows through the low resistors of bridge R1-R2-R3 is deviated to the input of amplifier 5 to charge the gate capacitor of the differential stage generally included by the amplifier. During this transient state, the ratio of the resistive bridge is thus not maintained. As a result, amplifier 5 only recovers a balance between its inputs with a delay associated, for example, with the magnitude of the input gate capacitance. This delay causes, when the switching occurs from the lower level to the upper level, an overvoltage on output Vout. The transient state progressively disappears by having voltage Vout decrease to reach the steady state.
It should be noted that delays may originate from other circuit stages, for example, other stages of amplifier 5. This depends on the regulator structure and what has been discussed for the input response time of amplifier 5 after a level change order of course also applies for any response time of the circuit downstream of input 8.
It should also be noted that the same problem may arise upon a switching from the upper level to the lower level, in the presence of a delay due, for example, to the discharge time of the gate capacitor of the input differential stage of amplifier 5. In this case, an undervoltage occurs upon switching.
Overvoltages due to output voltage switchings of linear regulators occur when this switching increases the output voltage level and possible undervoltages occur when the switching decreases the output voltage. Such undervoltages and/or overvoltages can be disturbing in some applications, especially when precise output levels are desired.
It should be noted that the magnitude of the undervoltage or overvoltage depends on the magnitude of the capacitance(s) involved in the path of the signals in the circuit. Now, the capacitance(s) may have large values for other reasons. For example, for the differential input stage of amplifier 5, the gate capacitance can be on the order of one picofarad to ensure a stability further required by amplifier 5.
An example of application in which this type of problem can be encountered is the field of portable phones where linear regulators are used to supply the different telephone circuits. In this type of application, the precision tolerances required for circuit output supply voltages are plus or minus 3%. This low tolerance is difficult to maintain with conventional linear regulators of the type described hereabove.
The present invention aims at providing a novel solution for switching the output of a linear regulator between two levels.
The present invention more specifically aims at providing a solution that limits undervoltages and/or overvoltages at the regulator output.
The present invention also aims at providing a solution that is compatible with the conventional electric circuit of a linear regulator.
To achieve these and other objects, the present invention provides a method for controlling a linear regulator of the type including a power MOS transistor, controlled by a differential amplifier having a first input terminal receiving a reference voltage and a second input terminal receiving, via a switchable resistor circuit, the output voltage of the regulator, a smooth switching of said resistors being provided.
According to an embodiment of the present invention, applied to a regulator in which the resistors of a dividing bridge are switched by means of at least two MOS control transistors, inverted voltage ramps, the direction of which is determined by the switching direction, are applied on the respective gates of these transistors.
According to an embodiment of the present invention, the duration of the ramps is chosen to maintain, on the second input of the differential amplifier, a voltage level substantially corresponding to the level of the reference voltage even during switching phases, to avoid unbalancing the differential amplifier.
The present invention also provides a linear regulator of the type including a power MOS transistor, controlled by a differential amplifier having an input terminal receiving, via a circuit of resistors switchable by means of MOS control transistors, a voltage proportional to the output voltage provided by the regulator, and including at least two circuits for generating inverted ramps for controlling the respective gates of said control transistors.
According to an embodiment of the present invention, each ramp generation circuit includes, in series between two supply terminals, two transistors of opposite channel types, the midpoint of their series connection providing, via a storage capacitor, said voltage ramp.
According to an embodiment of the present invention, the power MOS transistor is of a first channel type, the MOS control transistors being of a second channel type.
According to an embodiment of the present invention, the power MOS transistor and the MOS control transistors are of a same channel type.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.